A wafer scale programmable systolic data processor
- 9 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 252-256
- https://doi.org/10.1109/ugim.1991.148160
Abstract
The authors describe the programmable systolic data processor (PSDP). The PSDP will enhance US Department of Defense (DoD) mission capabilities by extending signal and data processing speed/performance while reducing system size, weight, and power consumption. The characteristics of this architecture which make it opportune for building as a wafer-scale system include broad homogeneity, ease of redundancy, and limited physical interconnect bandwidth of wafer-scale integration (WSI) using a robust programmable systolic array processing architecture. Thus, it will provide unique onboard processing capabilities for DoD missions Author(s) Landis, D. Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA Yoder, J. ; Whittaker, D. ; Dobbins, T.Keywords
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