Wafer-level 3D manufacturing issues for streaming video processors
- 7 September 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The performance of both 2D and 3D implementations of a streaming video processor is presented incorporating 130 nm technology node parameters. The reduced memory access time predicted for the 4 MB L2 cache (0.9 ns for 3D and 1.65 ns for 2D) is indicative of performance advantages projected for 3D implementations of memory-intensive architectures.Keywords
This publication has 5 references indexed in Scilit:
- Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A three-dimensional stochastic wire-length distribution for variable separation of strataPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Comparison of key performance metrics in two- and three-dimensional integrated circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Speed and power scaling of SRAM'sIEEE Journal of Solid-State Circuits, 2000
- CACTI: an enhanced cache access and cycle time modelIEEE Journal of Solid-State Circuits, 1996