Research Challenges for On-Chip Interconnection Networks

Top Cited Papers

12 November 2007

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro

Vol. 27 (5) , 96-108
https://doi.org/10.1109/mm.2007.4378787

Abstract

On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems, the National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.

Keywords

This publication has 9 references indexed in Scilit:

Implementation and Evaluation of a Dynamically Routed Processor Operand Network
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2007
In-Network Cache Coherence
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2006
SPEC CPU2006 benchmark descriptions
ACM SIGARCH Computer Architecture News, 2006
A theory for deadlock-free dynamic network reconfiguration. Part I
IEEE Transactions on Parallel and Distributed Systems, 2005
Low-Latency Virtual-Channel Routers for On-Chip Networks
ACM SIGARCH Computer Architecture News, 2004
Networks on chips: a new SoC paradigm
Computer, 2002
Route packets, net wires
Published by Association for Computing Machinery (ACM) ,2001
Remote queues
Published by Association for Computing Machinery (ACM) ,1995
The message-driven processor: a multicomputer processing node with efficient mechanisms
IEEE Micro, 1992