A 50ns floating-point signal processor VLSI
- 24 March 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 11, 401-404
- https://doi.org/10.1109/icassp.1986.1169044
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- CHAMP: Chip Floor Plan for Hierarchical VLSI Layout DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Hierarchical Top-Down Layout Design Method for VLSI ChipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982