Delay balanced multipliers for low power/low voltage DSP core

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 36-37
https://doi.org/10.1109/lpe.1995.482454

Abstract

A simple but effective technique, which synchronizes the propagation of signals at each full adder stage, has cut the power dissipation of an array multiplier down to equal to or less than that of a Wallace-tree multiplier with a minimal penalty in performance and layout area. This delay balanced array multiplier is a strong candidate for low power and small area DSP core for portable equipment.

Keywords

DELAY
LOW VOLTAGE
DIGITAL SIGNAL PROCESSING
ADDERS
POWER DISSIPATION
CLOCKS
SYNCHRONIZATION
SPICE
CIRCUIT SIMULATION
LABORATORIES

This publication has 2 references indexed in Scilit:

Analysis and reduction of glitches in synchronous networks
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
A Suggestion for a Fast Multiplier
IEEE Transactions on Electronic Computers, 1964