An experimental 295 MHz CMOS 4K×256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

This publication has 2 references indexed in Scilit:

• A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
  IEEE Journal of Solid-State Circuits, 1993
• A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1991