An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors
- 1 April 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 30 (4) , 412-422
- https://doi.org/10.1109/4.375961
Abstract
A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 /spl mu/m CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4/spl times/ the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.<>Keywords
This publication has 2 references indexed in Scilit:
- A Wide-Bandwidth Low-Voltage Pll for Powerpc MicroprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A PLL clock generator with 5 to 110 MHz lock range for microprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003