A New J-K Flip-Flop for Synchronizers
- 1 December 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-26 (12) , 1277-1279
- https://doi.org/10.1109/tc.1977.1674789
Abstract
Anomalous gating of asynchronous signals in synchronizers and arbiter circuits may cause significant errors and system failures. Since the probability of logically undefined states at the output of flip-flops increases rapidly with clock rate, the errors were reduced by lower frequencies, at the price of severe time loss, until now. The paper presents a J-K flip-flop in which the duration of an oscillatory or metastable behavior is reduced by a factor of 5 to 15. In this flip-flop the switching of two gates is accelerated by tunnel diodes.Keywords
This publication has 2 references indexed in Scilit:
- Anomalous Behavior of Synchronizer and Arbiter CircuitsIEEE Transactions on Computers, 1973
- Time Loss Through Gating of Asynchronous Logic Signal PulsesIEEE Transactions on Electronic Computers, 1966