2K x 8 Bit Hi-CMOS Static RAM's
- 1 August 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (4) , 656-660
- https://doi.org/10.1109/JSSC.1980.1051451
Abstract
Two Hi-CMOS static RAM's with 2K word by 8 bit organization have been developed. These RAM's are fabricated with single polysilicon technology, which reduces processing costs. A novel J-FET powered static cell formed in the p well is used. The cell area is reduced to 80 percent that of the standard cell. Hi-CMOS well structure gives good immunity to alpha-particle-induced soft errors. These new RAM's have an address access time of 74 ns, an operating power dissipation of 200 mW,and a standby dissipation of 25 /spl mu/W.Keywords
This publication has 2 references indexed in Scilit:
- A high-speed low-power Hi-CMOS 4K static RAMIEEE Transactions on Electron Devices, 1979
- A high-speed, low-power Hi-CMOS 4K static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978