High-speed autozeroed CMOS comparator for multistep A/D conversion
- 1 November 1998
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 29 (11) , 845-853
- https://doi.org/10.1016/s0026-2692(97)00123-7
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Power-efficient metastability error reduction in CMOS flash A/D convertersIEEE Journal of Solid-State Circuits, 1996
- A 25-Ms/s 8-bit CMOS A/D converter for embedded applicationIEEE Journal of Solid-State Circuits, 1994
- Design techniques for high-speed, high-resolution comparatorsIEEE Journal of Solid-State Circuits, 1992
- A high-speed CMOS comparator with 8-b resolutionIEEE Journal of Solid-State Circuits, 1992
- A 12-b 5-Msample/s two-step CMOS A/D converterIEEE Journal of Solid-State Circuits, 1992
- A high-speed CMOS comparator for use in an ADCIEEE Journal of Solid-State Circuits, 1988
- A 100-MHz pipelined CMOS comparatorIEEE Journal of Solid-State Circuits, 1988
- A CMOS 8-Bit High-Speed A/D Converter ICIEEE Journal of Solid-State Circuits, 1985
- A monolithic charge-balancing successive approximation A/D techniqueIEEE Journal of Solid-State Circuits, 1979
- A 1 mV MOS comparatorIEEE Journal of Solid-State Circuits, 1978