A single chip parallel multiplier by MOS technology
- 1 March 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 37 (3) , 274-282
- https://doi.org/10.1109/12.2164
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Algorithms for Iterative Array MultiplicationIEEE Transactions on Computers, 1986
- A Compact High-Speed Parallel Multiplication SchemeIEEE Transactions on Computers, 1977
- Design of ion-implanted MOSFET's with very small physical dimensionsIEEE Journal of Solid-State Circuits, 1974
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964