On clustering of defects and yield of SMT assemblies

17 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 75-79 vol.1
https://doi.org/10.1109/iemt.1994.404688

Abstract

This paper describes a clustered yield model for complex Surface Mount Technology (SMT) assemblies. The model uses the negative binomial distribution of defects to calculate board yield after test. Manufacturing data validates that this model accurately predicts the clustering of defects and the yield predictions are significantly better than traditional binomial models.

Keywords

SURFACE-MOUNT TECHNOLOGY
ASSEMBLY
CIRCUIT FAULTS
TESTING
INTEGRATED CIRCUIT YIELD
PREDICTIVE MODELS
VIRTUAL MANUFACTURING
PRODUCTION
DESIGN FOR MANUFACTURE
YIELD ESTIMATION

This publication has 3 references indexed in Scilit:

Board test DFT model for computer products
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1992
The use and evaluation of yield models in integrated circuit manufacturing
IEEE Transactions on Semiconductor Manufacturing, 1990
Integrated circuit yield statistics
Proceedings of the IEEE, 1983