Interconnect scaling: signal integrity and performance in future high-speed CMOS designs

27 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 42-43
https://doi.org/10.1109/vlsit.1998.689191

Abstract

The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 /spl mu/m generations. We show crosstalk to be very important in scaled ULSI interconnects and steps such as reduced aspect ratios and asymmetric pitches should be used to ensure signal integrity.

Keywords

This publication has 2 references indexed in Scilit:

Interconnect Scaling Scenario Using A Chip Level Interconnect Model
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1997
Performance trends in high-end processors
Proceedings of the IEEE, 1995