Analysis of Asynchronous Circuits Under Different Delay Assumptions
- 1 December 1968
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-17 (12) , 1131-1143
- https://doi.org/10.1109/tc.1968.226879
Abstract
Abstract—Asynchronous circuits are analyzed from the stand- point of different constraints which may apply to the stray delays (zero-line delays, bounded delays, and the use of delay elements). The relationship between "hazard-free" sequential networks and "speed independent" circuits is illuminated. Speed independence is defined relative to a fundamental mode circuit (which in turn may be described by a flow table); the analysis is carried out from this stand- point. The allowed sequence graph may be used to detect critical races. A circuit is seen to be speed independent if and only if its circuit-derived excitation matrix has no 1-input change critical races. The generalization of the essential hazard has been studied in detail and is shown to be an obstacle to hazard-free realizations when line delays can be arbitrarily large.Keywords
This publication has 4 references indexed in Scilit:
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- Hazard Detection in Combinational and Sequential Switching CircuitsIBM Journal of Research and Development, 1965
- Hazards and Delays in Asynchronous Sequential Switching CircuitsIRE Transactions on Circuit Theory, 1959
- The map method for synthesis of combinational logic circuitsTransactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics, 1953