Delay and current estimation in CMOS gates using collapsing
- 31 August 1993
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 24 (5) , 485-495
- https://doi.org/10.1016/0026-2692(93)90117-w
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Simultaneous delay and maximum current calculation in CMOS gatesElectronics Letters, 1992
- Delay analysis of series-connected MOSFET circuitsIEEE Journal of Solid-State Circuits, 1991
- Estimation of maximum currents in MOS IC logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990