Model for conductance in dry-etch damaged n-GaAs structures

Abstract
A model for the effects of dry‐etch damage on the conductances of etched structures is developed. Expressions for defect distribution are obtained for top‐surface and sidewall damage. The expression for sidewall damage is used in the calculation of wire conductances. The model accounts accurately for changes in experimentally measured conductances of SiCl4‐etched n+‐GaAs wires with variations in material carrier concentration, epilayer thickness, and etch time/depth. The analysis indicates that defects are created at a significant rate at sidewalls as compared to top surfaces.