Compact signed-digit adder using multiple-valued logic

This publication has 14 references indexed in Scilit:

• Prospects of multiple-valued associative VLSI processors
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Circuit simulation of resonant tunneling devices using NDR-SPICE
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture
  IEEE Journal of Solid-State Circuits, 1996
• Device and circuit simulation of quantum electronic devices
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
• Dynamic hysteresis of the RTD folding circuit and its limitation on the A/D converter
  IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1992
• Operating CMOS after a Si-MBE process: a precondition for future three-dimensional circuits
  IEEE Electron Device Letters, 1990
• Si/SiGe resonant tunnelling devices separated by surrounding polysilicon
  Electronics Letters, 1989
• A 32*32-bit multiplier using multiple-valued MOS current-mode circuits
  IEEE Journal of Solid-State Circuits, 1988
• The Prospects for Multivalued Logic: A Technology and Applications View
  IEEE Transactions on Computers, 1981
• Signed-Digit Numbe Representations for Fast Parallel Arithmetic
  IEEE Transactions on Electronic Computers, 1961