An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture
- 1 June 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (6) , 773-783
- https://doi.org/10.1109/4.509863
Abstract
No abstract availableKeywords
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