A 300 kbit bubble memory chip with planar structure
- 1 March 1978
- journal article
- conference paper
- Published by AIP Publishing in Journal of Applied Physics
- Vol. 49 (3) , 1930-1932
- https://doi.org/10.1063/1.324807
Abstract
A 300 kbit bubble memory chip has been designed based on 3 μm bubble technology. Nominal circuit period is 14 μm and chip size is 9.8 mm×9.6 mm. A gap-tolerant design is fully employed, such as, asymmetric half-disk propagation pattern, half-disk transfer gate, a novel asymmetric-chevron stretcher, etc. The chip is fabricated using a new planar process solving step-coverage problems to achieve good process yield. A typical bias field margin of 18 Oe is obtained at 55 Oe with a triangular wave drive.This publication has 5 references indexed in Scilit:
- 68 kbit capacity 16 µm-period magnetic bubble memory chip design with 2 µm minimum featuresIEEE Transactions on Magnetics, 1976
- Planar processing for magnetic bubble devicesIEEE Transactions on Magnetics, 1976
- Gap tolerant bubble propagation circuitIEEE Transactions on Magnetics, 1976
- Long-term testing of 68 kbit bubble device chipsIEEE Transactions on Magnetics, 1976
- Fabrication of large bubble circuitsIEEE Transactions on Magnetics, 1973