Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity

This publication has 12 references indexed in Scilit:

• Sequential Redundancy Identification Using Verification Techniques
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Removal of redundancy in logic circuits under classification of undetectable faults
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Test generation for synchronous sequential circuits based on fault extraction
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Test generation for synchronous sequential circuits using multiple observation times
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Classification of faults in synchronous sequential circuits
  IEEE Transactions on Computers, 1993
• The multiple observation time test strategy
  IEEE Transactions on Computers, 1992
• On removing redundancy in sequential circuits
  Published by Association for Computing Machinery (ACM) ,1991
• NOVA: state assignment of finite state machines for optimal two-level logic implementations
  Published by Association for Computing Machinery (ACM) ,1989
• MIS: A Multiple-Level Logic Optimization System
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
• Scan Design Using Standard Flip-Flops
  IEEE Design & Test of Computers, 1987