From recursive algorithm to parallel VLSI accelerator: a hierarchical design system with testbed

This publication has 5 references indexed in Scilit:

• A design method of systolic arrays under the constraint of the number of the processors
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Analysis and modeling of sequential iterative algorithms for parallel and pipeline implementations
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Automatic design and partitioning of systolic/wavefront arrays for VLSI
  Circuits, Systems, and Signal Processing, 1988
• A Novel VLSI System Of Linear Equations Solver For Real-Time Signal Processing
  Published by SPIE-Intl Soc Optical Eng ,1986
• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
  IEEE Transactions on Computers, 1986