Cell Multiprocessor Communication Network: Built for Speed
Top Cited Papers
- 5 July 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 26 (3) , 10-23
- https://doi.org/10.1109/mm.2006.49
Abstract
Multicore designs promise various power-performance and area-performance benefits. But inadequate design of the on-chip communication network can deprive applications of these benefits. To illuminate this important point in multicore processor design, the authors analyze the cell processor's communication network, using a series of benchmarks involving various DMA traffic patterns and synchronization protocolsKeywords
This publication has 9 references indexed in Scilit:
- Application of full-system simulation in exploratory system design and developmentIBM Journal of Research and Development, 2006
- QsNetII: Defining High-Performance Network DesignIEEE Micro, 2005
- Introduction to the Cell multiprocessorIBM Journal of Research and Development, 2005
- Power Efficient Processor Architecture and The Cell ProcessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Trends toward on-chip networked microsystemsInternational Journal of High Performance Computing and Networking, 2005
- Optimizing pipelines for power and performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The future of CMOS technologyIBM Journal of Research and Development, 2000
- Hitting the memory wallACM SIGARCH Computer Architecture News, 1995
- “Hot spot” contention and combining in multistage interconnection networksIEEE Transactions on Computers, 1985