Optimizing pipelines for power and performance
- 26 June 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 18 references indexed in Scilit:
- Select-free instruction scheduling logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- CPAM: a common power analysis methodology for high-performance VLSI designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delaysACM SIGARCH Computer Architecture News, 2002
- Power-aware microarchitecture: design and modeling challenges for next-generation microprocessorsIEEE Micro, 2000
- Deep submicron microprocessor design issuesIEEE Micro, 1999
- Environment for PowerPC microarchitecture explorationIEEE Micro, 1999
- Energy dissipation in general purpose microprocessorsIEEE Journal of Solid-State Circuits, 1996
- Circuit and architecture trade-offs for high-speed multiplicationIEEE Journal of Solid-State Circuits, 1991
- Optimal pipeliningJournal of Parallel and Distributed Computing, 1990
- Optimal pipelining in supercomputersACM SIGARCH Computer Architecture News, 1986