Configuration of boundary scan chain for optimal testing of clusters of non boundary scan devices
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Testing of boards containing a mixture of boundary scan components and clusters of non-boundary scan devices is considered. If a tester cannot contact the non-scan circuitry, the inputs and outputs of onboard boundary scan devices may be used as virtual tester pins. In this case, the time for testing the clusters depends on how the boundary scan chips are connected into a longer scan chain. A technique for configuring a chain of boundary scan chips to minimize the test time for clusters is presented.Keywords
This publication has 5 references indexed in Scilit:
- Test Generation: A Boundary Scan Implementation for Module Interconnect TestingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channelsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An optimal scheduling algorithm for testing interconnect using boundary scanJournal of Electronic Testing, 1991
- IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current statusJournal of Electronic Testing, 1991
- Designing and implementing an architecture with boundary scanIEEE Design & Test of Computers, 1990