Soft-programmable bypass switch design for defect-tolerant arrays

This publication has 9 references indexed in Scilit:

• The technology of laser formed interactions for wafer scale integration
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A wafer-scale FFT processor featuring a repeatable building block
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A reconfigurable wafer scale array for image processing
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Yield analysis for fault-tolerant arrays
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Fault-tolerant array processors using single-track switches
  IEEE Transactions on Computers, 1989
• Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay
  IEEE Journal of Solid-State Circuits, 1988
• Wafer-scale integration and two-level pipelined implementations of systolic arrays
  Journal of Parallel and Distributed Computing, 1984
• Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement
  IBM Journal of Research and Development, 1980
• Wafer-scale integration-a fault-tolerant procedure
  IEEE Journal of Solid-State Circuits, 1978