Limits to binary logic switch scaling-a gedanken model
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- 1 November 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 9 (11) , 1934-1939
- https://doi.org/10.1109/jproc.2003.818324
Abstract
In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation." We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.Keywords
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