64 kB sum-addressed-memory cache with 1.6 ns cycle and 2.6 ns latency

27 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 350-351
https://doi.org/10.1109/isscc.1998.672519

Abstract

This circuit combines a sum-addressed-memory (SAM) cache with delayed-reset logic circuitry, enabling cache access with a two-cycle-latency for a 6OO MHz third-generation superscalar processor implementing the Sparc V9 64b architecture.

Keywords

DELAY
DECODING
CIRCUITS
LOGIC TESTING
LOGIC DESIGN
PERFORMANCE EVALUATION
TIMING
LOGIC DEVICES
SUN
MICROELECTRONICS

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