Pipeline interleaving design for FIR, IIR, and FFT array processors

This publication has 7 references indexed in Scilit:

• A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor
  IEEE Journal of Solid-State Circuits, 1989
• Programmable DSP architectures. II
  IEEE ASSP Magazine, 1989
• A VLSI signal processor with complex arithmetic capability
  IEEE Transactions on Circuits and Systems, 1988
• A multiple-access pipeline architecture for digital signal processing
  IEEE Transactions on Computers, 1988
• Pipeline interleaved programmable DSP's: Architecture
  IEEE Transactions on Acoustics, Speech, and Signal Processing, 1987
• A 2-μm CMOS 8-MIPS digital processor with parallel processing capability
  IEEE Journal of Solid-State Circuits, 1986
• CUSP: A 2-μm CMOS Digital Signal Processor
  IEEE Journal of Solid-State Circuits, 1985