Bi-level reconfigurations of fault tolerant arrays in bi-modal computational environments

Abstract
Fault-tolerant architectures and algorithms are studied for processor arrays which are subject to computational loads that alternate between two phases-a strict phase, characterized by a heavy load and strict constraints on response time, and a relaxed phase, characterized by a light load and relatively relaxed constraints on response time. Under this type of load, a bilevel algorithm may be applied to reconfigure the system after faults. Specifically, at one level, called the fast response level, a local distributed fault-tolerant algorithm is used during the strict phase to achieve fast fault recovery at the expense of possible rapid degradation in the potential to tolerate future faults. In order to minimize the effect of this degradation, a second level, called the optimization level, is added. At that level, a global, relatively slow reorganization algorithm is applied during the relaxed phase to restore the system into a shape that ensures adequate fault-tolerance capability in the remaining part of the system's mission. Three examples are given for bilevel reconfiguration algorithms that emphasize three different restoration criteria.

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