A 4K CMOS erasable PROM
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 677-680
- https://doi.org/10.1109/JSSC.1978.1051118
Abstract
A high performance ultraviolet erasable complementary MOS PROM is described. Microwatt standby power is achieved by utilizing synchronous design on an ion-implanted silicon-gate CMOS technology. The device can operate with a single voltage supply from 4 to 11 V while still maintaining TTL compatibility on all address inputs, or with two supplies allowing under 200 ns access time with both TTL compatible address and output levels. On-chip address latches and high noise immunity are some of the other features that would simplify system design using the CMOS EPROM. Programming is by avalanche injection of electrons into selected floating gates. Single-location programming and high programming duty cycle reduce programming time to less than 30 s per device.Keywords
This publication has 2 references indexed in Scilit:
- MEMORY BEHAVIOR IN A FLOATING-GATE AVALANCHE-INJECTION MOS (FAMOS) STRUCTUREApplied Physics Letters, 1971
- Effect of junction curvature on breakdown voltage in semiconductorsSolid-State Electronics, 1966