A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter

This publication has 2 references indexed in Scilit:

• A semidigital dual delay-locked loop
  IEEE Journal of Solid-State Circuits, 1997
• A monolithic CMOS 10 MHz DPLL for burst-mode data retiming
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1990