Two‐dimensional numerical analysis of gaas MESFET with a p‐buffer layer

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Abstract
To suppress the threshold voltage shift of GaAs MESFET's in a shorter channel region, a two‐dimensional numerical analysis of the FET structure with a p‐buffer layer is carried out. As a result of the analysis, it is clarified that the insertion of the p‐buffer layer is effective in preventing the carrier penetration in the substrate. In analyzing the electrical properties as a function of the buffer layer thickness, it is found that the substrate current which flows beneath the p‐channel layer, decreases with an increase in the buffer layer thickness and that the threshold voltage shift is suppressed with the increase. As the buffer layer thickness increases, the transconductance increases. Moreover, as the buffer layer thickness increases, the gate‐substrate capacitance increases. Therefore, to obtain a high cutoff frequency, it is necessary to optimize the buffer layer thickness.

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