A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology
- 1 June 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (3) , 346-353
- https://doi.org/10.1109/jssc.1980.1051397
Abstract
A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle limitations when compared to conventional p-channel Al-gate MNOS memories. The 16 kbit chip shows improved features: fast access time of 140 ns, fast program time of 1 ms, fast erase time of 100 ms, and low power dissipation of 210 mW. New high voltage devices and circuits are used to obtain high breakdown voltage, resulting in a wide margin for the program voltage supply pin. This device, fully pin-compatible with the 16 kbit EPROM (UV erasable PROM), outperforms currently used EPROMs as well as conventional MNOS memories in almost all respects.Keywords
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