A single chip 80b floating point processor
- 23 March 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- CHAMP: Chip Floor Plan for Hierarchical VLSI Layout DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- An integrated modular and standard cell IC design methodPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Hierarchical Top-Down Layout Design Method for VLSI ChipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982