Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, named FlowSYN, uses the global combinatorial optimization techniques to guide the Boolean synthesis process during depth minimization. The combinatorial optimization is achieved by computing a series of minimum cuts of fixed heights in a network based on fast network flow computation, and the Boolean optimization is achieved by efficient OBDD-based implementation of functional decomposition. The experimental results show that FlowSYN improves FlowMap in terms of both the depth and the number of LUTs in the mapping solutions. Moreover, FlowSYN also outperforms the existing FPGA synthesis algorithms for depth minimization.Keywords
This publication has 11 references indexed in Scilit:
- Routability-driven technology mapping for lookup table-based FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Performance directed synthesis for table look up programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Logic synthesis for programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Chortle: a technology mapping program for lookup table-based field programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On area/depth trade-off in LUT-based FPGA technology mappingPublished by Association for Computing Machinery (ACM) ,1993
- Performance directed technology mapping for look-up table based FPGAsPublished by Association for Computing Machinery (ACM) ,1993
- BDD based decomposition of logic functions with application to FPGA synthesisPublished by Association for Computing Machinery (ACM) ,1993
- An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Technology mapping of lookup table-based FPGAs for performancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Minimization Over Boolean GraphsIBM Journal of Research and Development, 1962