Routability-driven technology mapping for lookup table-based FPGAs
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An algorithm for technology mapping of lookup-table-based field-programmable gate arrays is presented. It has the capability of producing slightly more compact designs than some existing mappers, and it offers the flexibility of trading routability with compactness of a design. The algorithm is implemented in the Rmap program and routability is compared with that of two other mappers. It is found that Rmap can produce mappings with better routability characteristics, and it produces routable mappings when other mappers do not.<>Keywords
This publication has 10 references indexed in Scilit:
- Improved logic synthesis algorithms for table look up architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Logic synthesis for programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Chortle: a technology mapping program for lookup table-based field programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Routability-driven technology mapping for lookup table-based FPGA'sIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Flexibility of interconnection structures for field-programmable gate arraysIEEE Journal of Solid-State Circuits, 1991
- A heuristic method for FPGA technology mapping based on the edge visibilityPublished by Association for Computing Machinery (ACM) ,1991
- XmapPublished by Association for Computing Machinery (ACM) ,1991
- Technology mapping for a two-output RAM-based field programmable gate arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Stochastic Models for Wireability Analysis of Gate ArraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Two-dimensional stochastic model for interconnections in master slice integrated circuitsIEEE Transactions on Circuits and Systems, 1981