A reconfigurable VLSI array for reliability and yield enhancement
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The fault-tolerance scheme consists of two phases: testing and locating faults (fault diagnosis), and reconfiguration. The first phase uses an online error-detection technique that achieves a compromise between the space and time redundancy approaches. This technique reduces the rollback time considerably and is capable of detecting permanent as well as transient faults. Reconfiguration consists of mapping the function of the faulty processor element onto an adjacent nonfaulty neighbor, which is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. A reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.Keywords
This publication has 12 references indexed in Scilit:
- Fault-Tolerant Hamiltonicity of Augmented Cubes under the Conditional Fault ModelPublished by Springer Nature ,2009
- Reconfigurable architectures for VLSI processing arraysProceedings of the IEEE, 1986
- VLSI Array processorsIEEE ASSP Magazine, 1985
- Switching circuits for yield-enhancement of an array chipElectronics Letters, 1984
- Characterization and Testing of Physical Failures in MOS Logic CircuitsIEEE Design & Test of Computers, 1984
- On Area and Yield Considerations for Fault-Tolerant VLSI Processor ArraysIEEE Transactions on Computers, 1984
- Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI DesignsIEEE Transactions on Computers, 1982
- Concurrent Error Detection in ALU's by Recomputing with Shifted OperandsIEEE Transactions on Computers, 1982
- Introduction to the configurable, highly parallel computerComputer, 1982
- Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale IntegrationIEEE Transactions on Computers, 1980