Characterization and Testing of Physical Failures in MOS Logic Circuits
- 1 August 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 1 (3) , 76-86
- https://doi.org/10.1109/mdt.1984.5005655
Abstract
Studies indicate that the conventional stuck-at fault model is inadequate for modeling the effects of physical failures on MOS circuits. The authors illustrate various types of non-stuck-at behavior, such as indeterminate logic levels, timing errors, and alteration of logic functions. They discuss the generation of tests for detecting the failures in simple and complex MOS circuits. An advantage of testing for failures at the circuit level is that in some cases it may be possible to utilize the structural properties of the circuit to design a much simpler test set compared to one that is based on a gatelevel description of the circuit. The authors outline a methodology whereby functional fault models are derived by studying the effects of physical failures at the circuit level for functional modules.Keywords
This publication has 6 references indexed in Scilit:
- Fault Detection and Design For Testability of CMOS Logic CircuitsPublished by Springer Nature ,1988
- Test Generation for MOS Circuits Using D-AlgorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980
- Reaching Agreement in the Presence of FaultsJournal of the ACM, 1980
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978