Generation of Optimal Transition Count Tests
- 1 January 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-27 (1) , 36-41
- https://doi.org/10.1109/TC.1978.1674950
Abstract
The problem of generating minimum-length transition count (TC) tests is examined for combinational logic circuits whose behavior can be defined by an n-row fault table. Methods are presented for generating TC tests of length n+2 and 2n-1 for fault detection and fault location, respectively. It is shown that these tests are optimal with respect to the class of n-row fault tables in the sense that there exist n-row fault tables that cannot be covered by shorter TC tests. The practical significance of these tests is discussed.Keywords
This publication has 5 references indexed in Scilit:
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- A Note on Testing Logic Circuits by Transition CountingIEEE Transactions on Computers, 1977
- Transition Count Testing of Combinational Logic CircuitsIEEE Transactions on Computers, 1976
- Fault Testing and Diagnosis in Combinational Digital CircuitsIEEE Transactions on Computers, 1968
- An Algorithm for Selecting an Optimum Set of Diagnostic TestsIEEE Transactions on Electronic Computers, 1965