VLSI architectures for multiplication in GF(2/sup m/) for application tailored digital signal processors

24 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 55-64
https://doi.org/10.1109/vlsisp.1996.558299

Abstract

Finite field arithmetic plays an important role in coding theory, cryptography and their applications. Several hardware solutions using finite field arithmetic have already been developed but none of them are user programmable. This is probably one reason why BCH codes are not commonly used in mobile communication applications even though these codes have very desirable properties regarding burst error correction. This article presents architectures for multiplication in GF(2/sup m/) applicable to digital signal processors. First a method is proposed to build an array of gates for hardware multiplication in GF(2/sup m/). Then an approach is shown that combines the hardware of a typical standard binary arithmetic multiplier with a GF(2/sup m/) multiplier. Using this approach saves a considerable number of gates and decreases the bus load while increasing the latency of the standard binary multiplier unit only marginally. Finally, a solution of a combined 17/spl times/17 integer/GF(2/sup m/spl les/8/) multiplier is presented and discussed.

Keywords

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