Putting the fill unit to work: dynamic optimizations for trace cache microprocessors
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- A fill-unit approach to multiple instruction issuePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Trace cache: a low latency approach to high bandwidth instruction fetchingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The performance potential of data dependence speculation and collapsingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Improving trace cache effectiveness with branch promotion and trace packingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Alternative fetch and issue policies for the trace cache fetch mechanismPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-orderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Facilitating superscalar processing via a combined static/dynamic register renaming schemePublished by Association for Computing Machinery (ACM) ,1994
- SCISM: A scalable compound instruction set machineIBM Journal of Research and Development, 1994
- Performance benefits of large execution atomic units in dynamically scheduled machinesPublished by Association for Computing Machinery (ACM) ,1989
- Checkpoint repair for out-of-order execution machinesPublished by Association for Computing Machinery (ACM) ,1987