Modeling the "Effective capacitance" for the RC interconnect of CMOS gates
- 1 January 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 13 (12) , 1526-1535
- https://doi.org/10.1109/43.331409
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- Modeling The RC-interconnect Effects In A Hierarchical Timing AnalyzerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Modeling the driving-point characteristic of resistive interconnect for accurate delay estimationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- DC parameterized piecewise-function transistor models for bipolar and MOS logic stage delay evaluationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- RICEPublished by Association for Computing Machinery (ACM) ,1991
- Asymptotic waveform evaluation for timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Macromodeling CMOS circuits for timing simulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Macromodeling and Optimization of Digital MOS VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Switch-Level Delay Models for Digital MOS VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Signal Delay in RC Tree NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI ChipsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982