Simulation Of Digital Circuits In The Presence of Uncertainty
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Coded time-symbolic simulation using shared binary decision diagramPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Timing verification using HDTVPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Event suppression: improving the efficiency of timing simulation for synchronous digital circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuitsPublished by Association for Computing Machinery (ACM) ,1989