Promising storage capacitor structures with thin Ta/sub 2/O/sub 5/ film for low-power high-density DRAMs

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Abstract
To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO/sub 2//Ta/sub 2/O/sub 5//SiO/sub 2//poly-Si or poly-Si/Si/sub 3/N/sub 4//Ta/sub 2/O/sub 5//SiO/sub 2//poly-Si (SIS), (b) W/Ta/sub 2/O/sub 5//SiO/sub 2//poly-Si (MIS), and (c) W/Ta/sub 2/O/sub 5/W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO/sub 2/ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950 degrees C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950 degrees C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta/sub 2/O/sub 5/ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5- mu m*3.6- mu m stacked-capacitor DRAM cells.<>

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