A 240K transistor CMOS array with flexible allocation of memory and channels

1 January 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVIII, 124-125
https://doi.org/10.1109/isscc.1985.1156853

Abstract

A CMOS masterslice will be reported, covering the design of basic cells to accommodate both logic unit and memory cells, wiring channels allocated in discrete units and logic and memory blocks placed in arbitrary positions of a cell array. Implementation of a 16×16b parallel multiplier with 16b×64w SRAM and 16b×256w ROM will be compared.

Keywords

RANDOM ACCESS MEMORY
WIRING
LOGIC ARRAYS
CMOS LOGIC CIRCUITS
LOGIC GATES
LARGE-SCALE SYSTEMS
READ ONLY MEMORY
LABORATORIES
LOGIC DESIGN
LATCHES

This publication has 2 references indexed in Scilit:

A CMOS 12K gate array with flexible 10Kb memory
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984
A 20ns CMOS functionable gate array with a configurable memory
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983