Submicron channel MOS-IC technology
- 1 January 1979
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The development of a submicron channel length MOS IC with a channel length of 0.3 to 0.9μm will be reported. Typical delay time per gate was in the range of subnanosecond to 2ns and power dissipation per gate was 0.3- 0.7mW.Keywords
This publication has 2 references indexed in Scilit:
- A theoretical and experimental analysis of the buried-source VMOS dynamic RAM cellIEEE Transactions on Electron Devices, 1978
- A 920 gate DSA MOS mastersliceIEEE Journal of Solid-State Circuits, 1978