Silicon-on-Nothing (SON)-an innovative process for advanced CMOS
Top Cited Papers
- 1 November 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 47 (11) , 2179-2187
- https://doi.org/10.1109/16.877181
Abstract
A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.Keywords
This publication has 26 references indexed in Scilit:
- Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse ?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SON (silicon on nothing)-a new device architecture for the ULSI eraPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Highly suppressed short-channel effects in ultrathin SOI n-MOSFETsIEEE Transactions on Electron Devices, 2000
- Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFETJapanese Journal of Applied Physics, 1999
- Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET'sIEEE Electron Device Letters, 1994
- High performance ultrathin SOI MOSFET's obtained by localized oxidationIEEE Electron Device Letters, 1994
- Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistanceIEEE Electron Device Letters, 1994
- Scaling the Si MOSFET: from bulk to SOI to bulkIEEE Transactions on Electron Devices, 1992
- Silicon-on-Insulator TechnologyPublished by Springer Nature ,1991
- Subthreshold slope of thin-film SOI MOSFET'sIEEE Electron Device Letters, 1986