Hybrid latch flip-flop with improved power efficiency
- 8 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase.Keywords
This publication has 2 references indexed in Scilit:
- Flow-through latch and edge-triggered flip-flop hybrid elementsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systemsIEEE Journal of Solid-State Circuits, 1999