Grain boundary and dislocation effects on the PV performance of high-purity silicon
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 101-105
- https://doi.org/10.1109/pvsc.1993.347071
Abstract
To quantify the effects of grain size and dislocation defects on the minority charge carrier lifetime /spl tau/ and photovoltaic (PV) efficiency of silicon, the authors grew high-purity, float-zoned (FZ) ingots with a range of grain sizes from single crystalline (dislocated and dislocation-free) down to 4/spl times/10/sup -4/ cm/sup 2/. In situ ingot cooling rates of 18/spl deg/ and 89/spl deg/C min/sup -1/ were used. Bulk ingot /spl tau/ ranged from less than 30 /spl mu/s for the multicrystalline ingots to 2,500 /spl mu/s for the dislocation-free crystals. Wafers from different positions in the ingots were used for /spl tau/ measurements and the fabrication of mesa-isolated, 0.04-cm/sup 2/ diagnostic PV device structures. They found that /spl tau/ decreased to 4 /spl mu/s and normalized solar cell efficiency decreased to 0.6 for the smallest average grain areas (4/spl times/10/sup -4/ cm/sup 2/).<>Keywords
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