A 15 b 1 Ms/s digitally self-calibrated pipeline ADC
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A digital calibration technique based on radix 1.93 that can be applied to pipeline or cyclic ADC (analog-to-digital converter) architectures is presented. An important advantage of this design is that calibration is performed in the digital domain, so that no extra analog circuitry, such as weighted capacitor arrays, and no extra clock cycles are needed. This calibration automatically accounts for capacitor mismatch, capacitor nonlinearity, charge injection, finite op-amp gain, and comparator offset. The fully differential pipeline ADC is implemented in an 11-V, 4 GHz, 2.4- mu m BiCMOS process.<>Keywords
This publication has 5 references indexed in Scilit:
- A high-frequency fully differential BiCMOS operational amplifierIEEE Journal of Solid-State Circuits, 1991
- A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converterIEEE Journal of Solid-State Circuits, 1988
- A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheralIEEE Journal of Solid-State Circuits, 1987
- Reference refreshing cyclic analog-to-digital and digital-to-analog convertersIEEE Journal of Solid-State Circuits, 1986
- A ratio-independent algorithmic analog-to-digital conversion techniqueIEEE Journal of Solid-State Circuits, 1984